Download Analog Circuit Design - High-Speed Clock And Data Recovery, by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier PDF

By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier

Analog Circuit layout includes the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and beneficial layout rules within the region of analog circuit layout. every one half is gifted through six specialists in that box and cutting-edge info is shared and overviewed. This booklet is quantity 17 during this winning sequence of Analog Circuit layout.

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Extra info for Analog Circuit Design - High-Speed Clock And Data Recovery, High-Performance Amplifiers, Power Management

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4. K. J. Wong, C. K. Yang, “A Serial-Link Transceiver with Transition Equalization”, ISSCC Dig. of Tech. Papers, pp. 82–83, Feb. 2006. 5. Fibre Channel, “Physical Interface-4 (FC-PI-4)”, Int. Committee for Information Technology Standardization (INCITS), Rev. 7, Sept. 2007. 6. R. Kajley, P. Hurst, “A Mixed-Signal Decision-Feedback Equalizer That Uses a Look-Ahead Architecture”, IEEE J. Solid-State Circuits, Vol. 32, No. 3, March 1997. 7. S. Gondi, B. Razavi, “Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers”, IEEE J.

41, No. 8, August 2006. 10. K. Yamaguchi, K. , “12 Gb/s Duobinary Signaling with x2 Oversampled Edge Equalization”, ISSCC Dig. of Tech. Papers, pp. 70–71, Feb. 2005. 11. J. H. Sinsky, M. , “High-Speed Electrical Backplane Transmission Using Duobinary Signaling”, IEEE Trans. On Microwave Theory and Techniques, Vol. 53, No. 1, January 2005 12. V. Stojanovic, A. , “Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver With Adaptive Equalization and Data Recovery”, IEEE J. Solid-State Circuits, Vol.

2 not equalized A+ A+ a) Clock not suppressed + b) Fig. 26 Optimal decision point in a channel that is not duobinary Fig. 27 Equivalence between DB logic and LA DFE logic 1) DFE: “1”; DB “1” Eg: prev. bit 1 A+ DFE selects this sampler B+ 3) DFE: “0”; DB negates the bit -> 0 2) DFE: “0”; DB “0” The three possible signal levels, either analyzed by a duobinary logic or by a DFE look-ahead logic, result in the same final decision. This leads to the conclusion that the look-ahead DFE can still receive duobinary signaling, once the proper phase and sampling thresholds are adopted.

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